The present invention relates generally to semiconductor device processing and, more particularly, to a method for reducing line edge roughness of oxide material using chemical oxide removal.
In the semiconductor industry, there is a continuing trend toward higher device densities by scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller feature sizes are required. These feature sizes may include, for example, the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various device structures.
The need for implementing small features with close spacing between adjacent features requires high-resolution photolithographic processes. Generally speaking, lithography refers to processes for pattern transfer between various media. More specifically, lithography is a technique used for integrated circuit fabrication in which a silicon slice (i.e., the wafer) is coated uniformly with a radiation-sensitive film (the resist). Then, an exposing source (such as optical light, x-rays, for example) illuminates selected areas of the surface through an intervening master template (i.e., the mask) for a particular pattern. Exposure of the coating through such a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The goal of a high performance lithography system is to provide a high resolution, repeatable system that reduces the linewidth of the features produced thereby. In addition to providing small, repeatable linewidths, it is also desirable to provide linewidth uniformity across the image field. In other words, it is desirable to provide a lithography system in which a designer can expect the linewidth of various features across the image field to fall within a predetermined range of a nominal, target value.
Unfortunately, as feature linewidths and the average linewidth variations associated with features continue to shrink, distinguishing the average linewidth variations that are due to the lithography system from the linewidth variations due to other phenomena becomes increasingly difficult. One such phenomenon is what is known in the art as “line edge roughness” (LER), which refers to the irregularities or deviations from the mean at the edge of the line and at the sidewalls of patterned features.
LER occurring in patterned features may be caused, for example, by a corresponding LER within an overlying photoresist, which is used as a mask for the patterning of the features. LER in photoresist masks may also caused by various factors such as, for example, LER on the chrome patterns which reside on the reticle (often called mask edge roughness), the image contrast of the system used in generating the photomask pattern, the plasma etch with which the photoresist pattern is formed, the photoresist material properties and chemistry and the photoresist processing scheme. Regardless of the specific cause(s) of the LER in the lithography process, the LER is subsequently transferred into the underlying film (e.g., metal, polysilicon, etc.). In addition to the original LER in the photoresist mask, the plasma etch used in subsequently patterning the underlying film further contributes to the LER of the patterned feature.
It will thus be appreciated that LER can impact the process control, for example, during gate patterning of a VLSI device. As the linewidth is scaled down in the semiconductor device, any line edge roughness (LER) introduced during gate patterning contributes more and more to the off-state leakage budget and short channel effect control. Accordingly, it is desirable to be able to reduce the LER of a resulting structure, such as a polysilicon gate line. Moreover, if the LER could be reduced without necessarily having to employ stricter lithographic processes, further benefits (such as higher speed devices) would result.